Basically all you need is 2D DMA which matches the interlacing. Each channel gets its own memory location. You will need to use ping-pong to keep it going. Another DMA channel is likely required to increase the depth of these FIFOs. Using PIO state machines should manage this. Overall you will end up in some kind of trigger transport. (125MHz is likely going to limit the sample rate. The CPU may actually be faster.) PIO would save a lot of memory operations and memory space, but may require more DMA channels.
1D:
Slave DMA who just does single transfers.
2D:
List of ADC channel transfers. (To memory if three DMAs or to PIO if using PIO.)
3D:
List of lists, which repeats from ping-pong or a loop in the list. (If you using only three DMAs.)
Standard FIFO DMA transfer from PIO to memory. (If you using PIO.)
1D:
Slave DMA who just does single transfers.
2D:
List of ADC channel transfers. (To memory if three DMAs or to PIO if using PIO.)
3D:
List of lists, which repeats from ping-pong or a loop in the list. (If you using only three DMAs.)
Standard FIFO DMA transfer from PIO to memory. (If you using PIO.)
Statistics: Posted by dthacher — Mon Feb 12, 2024 1:36 pm